1. Field of the Invention
The present invention relates to a driving apparatus for a plasma display panel and an image processing method thereof, and in particular, to a driving apparatus for plasma display panel and an image processing method thereof that results in reduced power consumption without flickers.
2. Description of the Related Art
Recently, flat panel displays, such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel (PDP) have been actively developed. The PDP is advantageous over other flat panel displays in regard to its high luminance, high luminous efficiency, and wide viewing angle.
A PDP displays an image by activating phosphor by ultraviolet (UV) rays generated by a discharge of an inert gas, e.g., He+Ne, He+Xe, or He+Ne+Xe. Such a PDP is classified into a direct current (DC) type or an alternating current (AC) type according to patterns of waveforms of driving voltages applied thereto and discharge cell structures thereof.
The DC PDP displays an image by applying a predetermined driving waveform to electrodes exposed to a discharge space. Since a DC PDP allows a direct current to flow through the discharge space while a voltage is applied to the exposed electrodes, such a DC PDP problematically requires a resistance for limiting the current. On the other hand, the AC PDP has electrodes covered with a dielectric layer that forms a capacitor to limit the current and protects the electrodes from the impact of ions during discharge. Accordingly, an AC PDP typically has a longer lifetime than a DC PDP.
FIG. 1 is a partial perspective view of an AC PDP.
As shown in FIG. 1, a conventional AC PDP includes scan and sustain electrodes 4 and 5 formed on an upper substrate 1 and address electrodes 8 formed on a lower substrate 6. Each of the scan and sustain electrodes 4 and 5 includes a transparent electrode and a metal bus electrode. The metal bus electrode has narrower width than the transparent electrode, and is disposed at a side of the transparent electrode.
The transparent electrode is usually formed of indium-tin-oxide (ITO). The metal bus electrode is usually formed of metal such as chrome Cr, and is formed on the transparent electrode so as to reduce a voltage drop by the transparent electrode having high resistance.
An upper dielectric layer 2 and a protective layer 3 are formed on the upper substrate 1 having the scan and sustain electrodes 4 and 5 formed thereon. Wall charges generated by a plasma discharge are accumulated on the upper dielectric layer 2. The protective layer 3 protects the upper dielectric layer 2 from damages caused by sputtering during the plasma discharge, and enhances emission efficiency of secondary electrons.
A lower dielectric layer 7 and barrier ribs 9 are formed on the lower substrate 6 on which the address electrodes 8 are formed, and a phosphor layer 10 is formed on the lower dielectric layer 7 and a surface of the barrier ribs 9. The address electrodes 8 are formed in a direction crossing the scan and sustain electrodes 4 and 5. The barrier ribs 9 are formed linearly or in a lattice pattern (not shown), and prevents UV rays and visible light generated by a discharge from leaking into adjacent discharge cells. The phosphor layer 10 is excited by the UV rays generated by a plasma discharge, and produces red, green, or blue color. An inert gas mixture is contained in a discharge space 11 formed by the upper substrate 1, the lower substrate 6, and the barrier ribs 9. A discharge cell (which may also be referred to as a cell) 12 is formed at an intersection region of the address electrode 8 and a pair of one scan electrode 4 and one sustain electrode 5 that are disposed in parallel.
FIG. 2 illustrates an electrode arrangement of a PDP.
Referring to FIG. 2, address electrodes A1 to Am are disposed in a column direction. Scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are disposed in a row direction in pairs. Discharge cells are formed in an m×n matrix format, wherein a discharge cell 12 is formed at each area where one of the address electrodes A1-Am crosses a pair of the scan and sustain electrodes Y1-Yn and X1-Xn.
The PDP is driven by frames, where each frame is divided into a plurality of subfields having different numbers of light emitting periods in order to realize a time-division grayscale display. Each subfield includes a reset period for initializing every discharge cell, an address period for selecting turn-on cells (i.e., cells to be turned on), and a sustain period for realizing grayscales according to the number of discharges in the turn-on cells.
That is, as shown in FIG. 3, each of a plurality of subfields includes a reset period, an address period, and a sustain period. FIG. 3 illustrates an exemplary subfield arrangement wherein one frame includes eight subfields so as to realize 256 grayscales. The reset period and the address period of the subfields are of the same length independent of the subfields. However, the sustain periods increase in ratios of 2n (n=0,1,2,3,4,5,6,7) according to subfields, so as to realize grayscales.
For example, in order to realize a grayscale of level 3 at a specific discharge cell, the specific cell is discharged during first and second subfields SF1 and SF2. In addition, in order to realize a grayscale of level 127 at a specific discharge cell, the specific cell is discharged during first through seventh subfields SF1-SF7. That is, 256 grayscales of an image are realized in a PDP by a combination of subfields having different light emitting periods.
According to such a conventional PDP, subfields that do not contribute to grayscales are also driven by the reset period, the address period, and the sustain period, and accordingly, power consumption becomes problematically wasteful. For a detailed example, the grayscale of the level 3 is realized by the first and second subfields SF1 and SF2. That is, for the grayscale of the level 3, the third to eighth subfields SF3-SF8 do not contribute to the grayscale. However, in this case, the reset, address, and sustain periods are also performed in the third to eighth subfields SF3-SF8 that do not contribute to the grayscale, and accordingly unnecessary switching operations are performed, thereby causing wasteful power consumption.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention, and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known in this country to a person of ordinary skill in the art.